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| 8-channel das with 18-bit, bipolar, simultaneous sampling adc data sheet AD7608 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011-2012 analog devices, inc. all rights reserved. features 8 simultaneously sampled inputs true bipolar analog input ranges: 10 v, 5 v single 5 v analog supply and 2.3 v to 5.25 v v drive fully integrated data acquisition solution analog input clamp protection input buffer with 1 m analog input impedance second-order antialiasing analog filter on-chip accurate reference and reference buffer 18-bit adc with 200 ksps on all channels oversampling capability with digital filter flexible parallel/serial interface spi/qspi?/microwire?/dsp compatible pin compatible solutions from 14-bits to 18-bits performance 7 kv esd rating on analog input channels 98 db snr, ?107 db thd low power: 100 mw standby mode: 25 mw 64-lead lqfp package applications power line monitoring and protection systems multiphase motor controls instrumentation and control systems multiaxis positioning systems data acquisition systems (das) companion products external references: adr421 , adr431 digital isolators: adum1402 , adum5000 , adum5402 voltage regulator design tool: adisimpower , supervisor parametric search complete list of complements on AD7608 product page table 1. high resolution, bi polar input, simultaneous sampling das solutions resolution single- ended inputs true differential inputs number of simultaneous sampling channels 18 bits AD7608 1 ad7609 8 16 bits ad7606 8 ad7606-6 6 ad7606-4 4 14 bits ad7607 8 functional block diagram v1 v1gnd r fb r fb r fb r fb r fb r fb r fb r fb r fb r fb r fb r fb r fb r fb r fb r fb 1m ? 1m ? clamp clamp second order lpf t/h v2 v2gnd 1m ? 1m ? clamp clamp second order lpf t/h v3 v3gnd 1m ? 1m ? clamp clamp second order lpf t/h v4 v4gnd 1m ? 1m ? clamp clamp second order lpf t/h v5 v5gnd 1m ? 1m ? clamp clamp second order lpf t/h v6 v6gnd 1m ? 1m ? clamp clamp second order lpf t/h v7 v7gnd 1m ? 1m ? clamp clamp second order lpf t/h v8 v8gnd 1m ? 1m ? clamp clamp second order lpf t/h 8:1 mux agnd busy frstdata convst a convst b reset range control inputs clk osc refin/refout ref select agnd os 2 os 1 os 0 d out a d out b rd/sclk cs par/ser sel v drive 18-bit sar digital filter parallel/ serial interface 2.5v ref refcapb refcapa serial parallel regcap 2.5v ldo regcap 2.5v ldo av cc av cc db[15:0] AD7608 08938-001 figure 1. 1 patent pending. www.datasheet.co.kr datasheet pdf - http://www..net/
AD7608 data sheet rev. a | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 companion products ....................................................................... 1 fun ctional block diagram .............................................................. 1 revision history ............................................................................... 2 general description ......................................................................... 3 sp ecifications ..................................................................................... 4 timing specifications .................................................................. 6 absolute maximum ratings .......................................................... 10 thermal resistance .................................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance characteristics ........................................... 14 terminology .................................................................................... 18 theory of operation ...................................................................... 19 converter details ....................................................................... 19 analog input ............................................................................... 19 adc transfer function ............................................................. 20 internal/external reference ...................................................... 21 typical connection diagram ................................................... 22 power - down modes .................................................................. 22 conversion control ................................................................... 23 digital interface .............................................................................. 24 parallel interface ( par /ser sel = 0) ...................................... 24 serial interface ( par /ser sel = 1) ......................................... 25 reading during conversion ..................................................... 25 digital filter ................................................................................ 26 layout guidelines ....................................................................... 30 outline dimensions ....................................................................... 32 ordering guide .......................................................................... 32 revision history 1/12 rev. 0 to rev. a changes to analog input ranges section 19 4/ 11 revision 0: initial versi on www.datasheet.co.kr datasheet pdf - http://www..net/ data sheet AD7608 rev. a | page 3 of 32 general description the AD7608 is an 18 - bit, 8 - channel simultaneous s ampling, analog - to - digital data acquisition system (das). the part contains analog input clamp protection, a second - order antialiasing filter, a track - and - hold amplifier, an 18 - bit charge redistribution successive approximation analog - to - digital converter (adc), a flexible digital filter, a 2.5 v reference and reference buffer, and high speed serial and parallel interfaces. the AD7608 operates from a single 5 v supply and can accommodate 10 v and 5 v true bipolar input signals while sampling at throug hput rates up to 200 ksps for all channels. the input clamp protection circuitry can tolerate vo ltages up to 16.5 v. the AD7608 has 1 m? analog input impedance regardless of sampling frequency. the single supply operation, on - chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies. the AD7608 antialiasing filter has a 3 db cutoff frequency of 22 khz and provides 40 db antialias rejection when sampling at 200 ksps. the flexible digital filter is pin driven, yields improvements in snr, and reduces the 3 db bandwidth. www.datasheet.co.kr datasheet pdf - http://www..net/ AD7608 data sheet rev. a | page 4 of 32 specifications v ref = 2.5 v external/internal, av c c = 4.75 v to 5.25 v, v drive = 2.3 v to 5.25 v; f sample = 200 ksps, t a = t min to t max , unless otherwise noted. 1 table 2. parameter test conditions/comments min typ max unit dynamic performance f in = 1 khz sine wave unless ot herwise noted signal - to - noise ratio ( snr ) 2 , 3 oversampling by 16; 10 v range; f in = 130 hz 98 99.5 db oversampling by 16; 5 v range; f in = 130 hz 95.5 97.5 db no oversampling; 10 v r ange 89.5 90.9 db no oversampling; 5 v range 88.5 90 db signal -to - (noise + distortion) (sinad) 2 no oversampling; 10 v range 88.5 90.5 db no oversampling; 5 v range 8 8 89 .5 db dynamic range no oversampling; 10 v range 91.5 db no oversampling; 5 v range 90.5 db total harmonic distortion (thd) 2 ?107 ? 95 db peak harmonic or spurious noise (sfdr) 2 ? 108 db intermodulation distortion (imd) 2 fa = 1 khz, fb = 1.1 khz second - order terms ?110 db third - order terms ? 106 db channel -to - channel isolation 2 f in on unselected channels up to 160 khz ? 95 db analog input filter full power bandwidth ?3 db, 10 v range 23 khz ?3 db, 5 v range 15 khz ?0.1 db, 10 v range 10 khz ?0.1 db, 5 v range 5 khz t group delay 10 v range 11 s 5 v range 15 s dc accuracy resolution no missing codes 18 bits differential nonlinearity 2 0.75 ? 0.99/ +2.6 lsb 4 integral nonlinearity 2 2.5 7.5 lsb total unadjusted error (tue) 10 v range 15 lsb 5 v range 40 lsb positive full - scale error 2 , 5 external reference 15 128 lsb internal reference 4 0 lsb positive full - scale error drift external reference 2 ppm/c internal reference 7 ppm/c positive full - scale error matching 2 10 v range 12 95 lsb 5 v range 30 128 lsb bipolar zero code error 2 , 6 10 v range 3. 5 24 lsb 5 v range 3.5 48 lsb bipolar zero code error drift 10 v range 10 v/c 5 v range 5 v/c bipolar zero code error matching 2 10 v range 3 30 lsb 5 v range 21 65 lsb negative full - scale error 2 , 5 external reference 1 5 128 lsb internal reference 40 lsb negative full - scale error drift external reference 4 ppm/c internal reference 8 ppm/c negative full - scale error matching 2 10 v range 12 95 lsb 5 v range 30 128 lsb www.datasheet.co.kr datasheet pdf - http://www..net/ data sheet AD7608 rev. a | page 5 of 32 parameter test conditions/comments min typ max unit analog input input voltage ranges range = 1 1 0 v range = 0 5 v analog input current 10 v; see figure 28 5.4 a 5 v; see figure 28 2.5 a input capacitance 7 5 pf input impedance 1 m reference input/output reference inpu t voltage range 2.475 2.5 2.525 v dc leakage current 1 a input capacitance 7 ref select = 1 7.5 pf reference output voltage refin/refout 2.49/ 2.505 v reference temperature coefficient 10 ppm/c logic inpu ts input high voltage (v inh ) 0.9 v drive v input low voltage (v inl ) 0.1 v drive v input current (i in ) 2 a input capacitance (c in ) 7 5 pf logic outputs output high voltage (v oh ) i source = 100 a v drive ? 0.2 v output low voltage (v ol ) i sink = 100 a 0.2 v floating - state leakage current 1 20 a floating - state output capacitance 7 5 pf output coding twos complement conversion rate convers ion time all eight channels included; see table 3 4 s track - and - hold acquisition time 1 s throughput rate per channel, all eight channels included 200 ksps power requirements av cc 4.75 5.25 v v drive 2.3 5.25 v i total digital inputs = 0 v or v drive normal mode (static) 16 22 ma normal mode (operational) 8 f sample = 200 ksps 20 27 ma standby mode 5 8 ma shutdown mode 2 11 a power dissipation normal mode (static) 80 115.5 mw normal mode (operational) 8 f sample = 200 ksps 100 142 mw standby mode 25 42 mw shutdown mode 10 58 w 1 temperature range for b version is ?40c to +85 c. 2 see the terminology section. 3 this specification applies when reading during a conversion or after a conversion. if reading during a conversion in parallel mode with v drive = 5 v, snr typically reduces by 1.5 db and thd by 3 db. 4 lsb means least significant bit. with 5 v input range, 1 lsb = 38.14 v. with 10 v input range, 1 lsb = 76.29 v. 5 these specifications include the full temperature range variation and contribution from the internal reference buffer but do not i nclude the error contribution from the external reference. 6 bipolar zero code error is calculated with respect to the analog input voltage. 7 sample tested during initial release to ensure compliance. 8 operational power/current figure includes contribut ion when running in oversampling mode. www.datasheet.co.kr datasheet pdf - http://www..net/ AD7608 data sheet rev. a | page 6 of 32 timing specification s a v cc = 4.75 v to 5.25 v, v drive = 2.3 v to 5.25 v, v ref = 2.5 v external reference/internal refe rence, t a = t min to t max , unless otherwise noted. 1 table 3. limit at t min , t max parameter min typ max unit description parallel/serial/byte mode t cycle 1/throughput rate 5 s parallel mode, reading during or af ter conversion; or serial mode: v drive = 3.3 v to 5.25 v, reading during a conversion using d out a and d out b lines 5 s serial mode reading during conversion; v drive = 2.7 v 10.5 s serial mode reading after a conversion; v drive = 2.3 v, d out a and d out b lines t conv conversion time 3.45 4 4.15 s oversampling off 7.87 9.1 s oversampling by 2 16.05 18.8 s oversampling by 4 33 39 s oversampling by 8 66 78 s oversampling by 16 133 158 s oversampling by 32 257 315 s oversamp ling by 64 t wake - up standby 100 s e e aa rising edge to convst x rising edge; power - up time from standby mode stby t wake - up shutdown internal reference 30 ms a a stby e e aa rising edge to convst x rising edge; power - u p time from shutdown mode external reference 13 ms a a stby e e aa rising edge to convst x rising edge; power - up time from shutdown mode t reset 50 ns reset high pulse width t os_setup 20 ns busy to os x pin setup time t os_hold 20 ns busy to os x pin hold time t 1 40 ns convst x high to busy high t 2 25 ns minimum convst x low pulse t 3 25 ns minimum convst x high pulse t 4 0 ns busy falling edge to a a cs e e aa falling edge setup time t 5 10f 9f 2 0.5 ms maximum del ay allowed between convst a, convst b rising edges t 6 25 ns maximum time between last a a cs e e aa rising edge and busy falling edge t 7 25 ns minimum delay between reset low to convst x high parallel/byte read operation t 8 0 ns a a cs e e aa to a a rd e e aa setup time t 9 0 ns a a cs e e aa to a a rd e e aa hold time t 10 a a rd e e aa low pulse width 16 ns v drive above 4.75 v 21 ns v drive above 3.3 v 25 ns v dri ve above 2.7 v 32 ns v drive above 2.3 v t 11 15 ns a a rd e e aa high pulse width t 12 22 ns a a cs e e aa high pulse width (see figure 5 ); a a cs e e aa and a a rd e e aa linked www.datasheet.co.kr datasheet pdf - http://www..net/ data sheet AD7608 rev. a | page 7 of 32 limit at t min , t max parameter min typ max unit description t 13 delay from a cs e a until db[15:0] three-state disabled 16 ns v drive above 4.75 v 20 ns v drive above 3.3 v 25 ns v drive above 2.7 v 30 ns v drive above 2.3 v t 14 3 data access time after a rd e a falling edge 16 ns v drive above 4.75 v 21 ns v drive above 3.3 v 25 ns v drive above 2.7 v 32 ns v drive above 2.3 v t 15 6 ns data hold time after a rd e a falling edge t 16 6 ns a cs e a to db[15:0] hold time t 17 22 ns delay from a cs e a rising edge to db[15:0] three-state enabled serial read operation f sclk frequency of serial read clock 23.5 mhz v drive above 4.75 v 17 mhz v drive above 3.3 v 14.5 mhz v drive above 2.7 v 11.5 mhz v drive above 2.3 v t 18 delay from a cs e a until d out a/d out b three-state disabled/delay from a cs e a until msb valid 15 ns v drive above 4.75 v 20 ns v drive above 3.3 v 30 ns v drive = 2.3 v to 2.7 v t 19 1 1 f 3 data access time after sclk rising edge 17 ns v drive above 4.75 v 23 ns v drive above 3.3 v 27 ns v drive above 2.7 v 34 ns v drive above 2.3 v t 20 0.4 t sclk ns sclk low pulse width t 21 0.4 t sclk ns sclk high pulse width t 22 7 sclk rising edge to d out a/d out b valid hold time t 23 22 ns a cs e a rising edge to d out a/d out b three-state enabled frstdata operation t 24 delay from a cs e a falling edge until frstdata three-state disabled 15 ns v drive above 4.75 v 20 ns v drive above 3.3 v 25 ns v drive above 2.7 v 30 ns v drive above 2.3 v t 25 ns delay from a cs e a falling edge until frstdata high, serial mode 15 ns v drive above 4.75 v 20 ns v drive above 3.3 v 25 ns v drive above 2.7 v 30 ns v drive above 2.3 v t 26 delay from a rd e a falling edge to frstdata high 16 ns v drive above 4.75 v 20 ns v drive above 3.3 v 25 ns v drive above 2.7 v 30 ns v drive above 2.3 v www.datasheet.co.kr datasheet pdf - http://www..net/ AD7608 data sheet rev. a | page 8 of 32 limit at t min , t max parameter min typ max unit description t 27 delay from a a rd e e aa falling edge to frstdata low 19 ns v drive = 3.3 v to 5.25 v 24 ns v drive = 2.3 v to 2.7 v t 28 delay from 16 th sclk falling edge to frstdata low 17 ns v drive = 3.3 v to 5.25 v 22 ns v drive = 2.3 v to 2.7 v t 29 24 ns delay from a a cs e e aa rising edge until frstdata three - state enabled 1 sample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. 2 the delay between the convst x signals was measured as the maximum time allowed while ensuring a <40 lsb performance matching between channel sets. 3 a buffer i s used on the data o utput pins for these measurements, which is equivalent to a load of 20 pf o n the output pins. timing diagrams t cycle t 3 t 5 t 2 t 4 t 1 t 7 t reset t conv convst a/ convst b convst a/ convst b busy cs reset 08938-002 figure 2 .convst x timing readi ng after a conversion t cycle t 3 t 5 t 6 t 2 t 1 t conv convst a/ convst b convst a/ convst b busy cs t 7 t reset reset 08938-003 figure 3 . convst x timing reading during a conversion data: db[15:0] frstdata cs rd in v alid v1 [17:2] v1 [1:0] v2 [17:2] v8 [17:2] v8 [1:0] v2 [1:0] t 10 t 8 t 13 t 24 t 26 t 27 t 14 t 11 t 9 t 16 t 17 t 29 08938-004 t 15 figure 4 . parallel mode separate a a cs e e aa and a a rd e e aa pulses www.datasheet.co.kr datasheet pdf - http://www..net/ data sheet AD7608 rev. a | page 9 of 32 data: db[15:0] frstdata cs, rd v1 [17:2] v1 [1:0] v2 [17:2] v2 [1:0] v7 [17:2] v7 [1:0] v8 [17:2] v8 [1:0] t 12 t 13 t 16 t 17 08938-005 figure 5 . a a cs e e aa and a a rd e e aa linked parallel mode sclk d out a, d out b frstdata cs db17 db16 db15 db1 db0 t 18 t 19 t 21 t 20 t 23 t 29 t 28 t 25 08938-006 t 22 figure 6 . serial read operation (channel 1) www.datasheet.co.kr datasheet pdf - http://www..net/ AD7608 data sheet rev. a | page 10 of 32 absolute maximum rat ings t a = 25c, unless otherwise noted. table 4. parameter rating av cc to agnd ?0.3 v to +7 v v drive to agnd ?0.3 v to av cc + 0.3 v analog input voltage to agnd 1 16.5 v digital input voltage to a gnd ?0.3 v to v drive + 0.3 v digital output voltage to a gnd ?0.3 v to v drive + 0.3 v refin to agnd ?0.3 v to av c c + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range b version ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c pb/sn temperature, soldering reflow (10 sec to 30 sec) 240 (+0)c pb - free temperature, soldering reflow 260 (+0)c esd (all pins except analog inputs) 2 kv esd (analog input pins only) 7 kv 1 transient currents of up to 100 ma do not cause scr latch - up. stresses above those listed under absolute maximum ratings ma y cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum ra ting conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. these specifications apply to a 4 - layer board. table 5 . thermal resistance package type ja jc unit 64- lead lqfp 45 11 c /w esd caution www.datasheet.co.kr datasheet pdf - http://www..net/ data sheet AD7608 rev. a | page 11 of 32 pin configuration an d function descripti ons AD7608 top view (not to scale) 64 63 62 61 60 59 58 57 v1gnd 56 55 54 53 52 51 50 49 v5 v4 v6 v3 v2 v1 pin 1 v7 v8 v2gnd v3gnd v4gnd v5gnd v6gnd v7gnd v8gnd db13 db12 db11 db14 v drive db1 17 18 19 20 21 22 23 24 25 agnd 26 27 28 29 30 31 32 db2 db3 db4 db5 db6 db7/d out a db9 db10 db8/d out b agnd av cc 1 3 4 frstdata 7 6 5 os 2 2 8 9 10 12 13 14 15 16 11 db0 busy convst b convst a range reset rd/sclk cs par/ser sel os 1 os 0 stby decoupling capacitor pin data output power supply analog input ground pin digital output digital input reference input/output db15 refin/refout 48 46 45 42 43 44 47 41 40 39 37 36 35 34 33 38 agnd av cc refgnd refcapa agnd agnd agnd refcapb refgnd regcap regcap av cc av cc ref select 08938-007 figure 7 . pin configuration table 6 . pin function descriptions pin no. type 12f 11f 1 mnemonic description 1, 37, 38, 48 p av cc analog supply voltage 4.75 v to 5.25 v. this supply voltage is applied to the internal front - end amplifiers and to the adc core. these supply pins should be decoupled to agnd. 2, 26, 35, 40, 41, 47 p agnd analog ground. this pin is the ground reference point for all analog circuitry on the AD7608 . all analog input signals and external reference signals should be referred to these pins. all six of these agnd pins shoul d connect to the agnd plane of a system. 5, 4, 3 di os [2: 0] oversampling mode pins. logic inputs. these inputs are used to select the oversampling ratio. os 2 is the msb control bit , while os 0 is the lsb control bit. see the digital filter section for further details on the oversampling mode of operation and table 8 for oversampling bit decoding. 6 di a a par e e aa /ser sel parallel/serial interface selection input. logic input. if this pin is tied to a logic low, the parallel interface is selected. if this pin is tied to a logic high, the serial interface is selected. in serial mode, the a a rd e e aa /sclk pin functions as the serial clock input. the db7/d out a and db8/d out b pin s function as serial data output s . when the serial interface is selected , db[15:9] and db[6:0] pins should be tied to gnd. 7 di a a stby e e stand by mode input. this pin is used to place the AD7608 into one of two power - down mod es: stand by mode or shutdown mode. the power - down mode entered depends on the state of the range pin as shown in table 7 . when in standby mode , all circuitry , except the on - chip reference regulators, and regulator buffers , is powe red down. when in shutdown mode, all circuitry is powered down. 8 di range analog input range selection. logic input. the polarity on this pin determines the input range of the analog input channels. if this pin is tied to a logic high, the analog input r ange is 10 v for all channels. if this pin is tied to a logic low, the analog input range is 5 v for all channels. a logic change on this pin has an immediate effect on the analog input range. changing this pin during a conversion is not recommended. se e the analog input section for more details. 9, 10 di convst a, convst b conversion start input a, conversion start input b. logic inputs. these logic inputs are used to initiate conversions on the analog input channels. for simu ltaneous sampling of all input channels, convst a and convst b can be shorted together and a single convert start signal applied. alternatively, convst a can be used to init iate simultaneous sampling for v1, v2, v3 , and v4 , and convst b can be used to ini tiate simultaneous samp ling on the other analog inputs (v5, v6, v7, and v8). this is only possible when oversampling is not switched on. wh en the convst a or convst b pin transitions from low to high, the front - end track - and - hold circuitry for their respec tive analog inputs is set to hold. this function allows a phase delay to be created inherently betw een the sets of analog inputs. www.datasheet.co.kr datasheet pdf - http://www..net/ AD7608 data sheet rev. a | page 12 of 32 pin no. type 12f 11f 1 mnemonic description 11 di reset reset input. when set to logic high, the rising edge of reset resets the AD7608 . once t wake - up has elapsed, t he part should receive a reset pulse after power up . the reset high pulse should be typically 100 ns wide. if a reset pulse is applied during a conversion , the conversion is aborted. if a reset pulse is applied during a read , the contents of the output regis ters resets to all zeros. 12 di a a rd e e aa /sclk parallel data read control input when parallel interface is selected ( a a rd e e aa )/ serial clock input w hen the serial interface is selected (sclk) . when both a a cs e e aa and a a rd e e aa are logic low in parallel mode, the output bus is enabled. in parallel mode, two a a rd e e aa pulses are required to read the full 18 bits of conversion results from each channel. the first a a rd e e aa pu lse outputs db[ 17:2] , the second a a rd e e aa pulse outputs db[1:0]. in serial mode, this pin acts as the serial clock input for data transfers. the a a cs e e aa falling edge takes the data output lines, d out a and d out b, out of three - state and clocks out the msb of the conversion result. the rising edge of sclk clocks all subsequent data bits onto the d out a and d out b serial data outputs . for further information , see the conversion control secti on. 13 di a a cs e e chip select. this active low logic input frames the data transfer. when both a a cs e e aa and a a rd e e aa are logic low in parallel mode, the output bus, db[15:0], is enabled and the conversion resu lt is output on the parallel data bus lines. in serial mode, the a a cs e e aa is used to frame the serial read transfer and clock out the msb of the serial output data. 14 do busy busy output. this pin transitions to a logic high after both con vst a and convst b rising edges and indicates that the conversion process has started. the busy output remains high until the conversion process for all channels is complete. the falling edge of busy signals that the conversion data is being latched into t he output data registers and is available to be read after a time t 4 . any data read while busy is high must be complete before the falling edge of busy occurs. rising edges on convst a or convst b have no effect while the busy signal is high. 15 do frstda ta digital output. the frstdata output signal indicates when the first channel, v1, is being read back on either the parallel or serial interface. when the a a cs e e aa input is high, the frstdata output pin is in three - state. the falling edge o f a a cs e e aa takes frstdata out of three - state. in parallel mode, the falling edge of a a rd e e aa corresponding to the result of v1 then sets the frstdata pin high indicating that the result from v1 is available on the output data bus. the frstdata output returns to a logic low following the third falling edge of a a rd e e aa . in serial mode, frstdata goes high on the falling edge of a a cs e e aa as this clocks out the msb of v1 on d out a. it returns low on the 18 th sclk falling edge after the a a cs e e aa falling edge. see the conversion control section for more details. 22 to 16 do db[6: 0] parallel output data bits, db6 to db0. when a a par e e aa /ser sel = 0, th ese pins act as three - state parallel digital output pins. when a a cs e e aa and a a rd e e aa are low, these pins are used to output db8 to db2 of the conversion result during the first a a rd e e aa pulse and output 0 during the second a a rd e e aa pulse. when a a par e e aa /ser sel = 1, these pins should be tied to gnd. 23 p v drive logic power supply input. the voltage (2.3 v to 5 .25 v) supplied at this pin determines the operating voltage of the interf ace. this pin is nominally at the same supply as the supply of th e host interface (that is, dsp and fpga). 24 do db7/d out a parallel output data bit 7 (db7)/serial interface data output pin (d out a). when a a par e e aa /ser sel = 0, this pin acts as a three - state parallel digital output pin . when a a cs e e aa and a a rd e e aa are low, this pin is used to output db9 of the conversion result. when a a par e e aa /ser sel = 1, this pin functions as d out a and outputs seri al conversion data. see the conversion control section for further details. 25 do db8/d out b parallel output data bit 8 (db8) /serial interface data output pin (d out b). when a a par e e aa /ser sel = 0, this pin acts as a three - state parallel digital output pin . when a a cs e e aa and a a rd e e aa are low, this pin is used to output db10 of the conversion result. when a a par e e aa /ser sel = 1, this pin functions as d out b and outputs serial c onversion data. see the conversion control section for further details. 31 to 27 do db[13:9] parallel output data bits, db13 to db9. when a a par e e aa /ser sel = 0, these pins act as three - state parallel digital output pins . when a a cs e e aa and a a rd e e aa are low, these pins are used to output db15 to db11 of the conversion result during the first a a rd e e aa pulse and output zero during the second a a rd e e aa pulse. whe n a a par e e aa /ser sel = 1 , these pins should be tied to gnd. 32 do/di db14 parallel output data bit 14 (db14 ) . when a a par e e aa /ser sel = 0, this pin act as three - state parallel digital ou tput pin. when a a cs e e aa and a a rd e e aa are low, this pin is used to output db16 of the conversion result during th e first a a rd e e aa pulse and db0 of the same conversion result during the second a a rd e e aa pulse. when a a par e e aa /ser sel = 1, this pins should be tied to gnd. 33 do/di db15 parallel output data bit 15 (db15) . when a a par e e aa /ser sel = 0, this pin acts as three - state parallel digital output pin. this pin is used to output db17 of the conversion result during the first a a rd e e aa pulse and db1 of the same conversion result during the second a a rd e e aa pulse. when a a par e e aa /ser sel = 1, this pins should be tied to gnd. www.datasheet.co.kr datasheet pdf - http://www..net/ data sheet AD7608 rev. a | page 13 of 32 pin no. type 12f 11f 1 mnemonic description 34 di ref select internal/external reference selection input. logic input. if this pin is set to logic high then the internal reference is selected and is enabled, if this pin is set to logic low then the internal reference is disabled and an external reference voltage must be applied to the refin/r efout pin. 36, 39 p regcap decoupling capacitor pins for voltage output from internal regulator. these output pins should be decoupled separately to agnd using a 1 f capacitor. the voltage on these output pins is in the range of 2.5 v to 2.7 v. 42 ref refin/ refout reference inpu t/reference output. the on - chip reference of 2.5 v is available on this pin for external use if the ref select pin is set to a logic high. alternatively, the inter nal reference can be disabled by setting the ref select pin to a logic low and an external re ference of 2.5 v can be applied to this input. see the internal/external reference section. decoupling is required on this pin for both the internal or external reference options. a 10 f capacitor should be applie d from this pin to ground close to the refgnd pins. 43, 46 ref refgnd reference ground pins. these pins should be connected to agnd. 44, 45 ref refcapa, refcapb reference buffer output force/sense pins. these pins must be connected together and decoupled to agnd using a low esr 10 f ceramic capacitor. 49, 51, 53, 55, 57, 59, 61, 63 ai v1 to v8 analog inputs. these pins are single - ended analog inputs. the analog input range of these channels is determined by the range pin. 50, 52, 54, 56, 58, 60, 62, 64 ai/ gnd v1gnd to v8gnd analog input ground pins. these pins correspond to the v1 to v8 analog input pins. connect a ll analog input agnd pins to the agnd plane of a system. 1 refers to classification of pin type; p denotes power, ai denotes analog input, ref denotes reference, di denotes digital input, do denotes digital output. www.datasheet.co.kr datasheet pdf - http://www..net/ AD7608 data sheet rev. a | page 14 of 32 typical performance characteristics ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10k 20k 30k 40k 50k 60k 70k 80k 90k 100k snr (db) input frequenc y (hz) 08938-008 a v c c , v d r i v e = 5 v i n t e r n a l r e f e r e n c e f s a m p l e = 200 k sps t a = 2 5c 10 v r a n g e s n r = 91 . 23 d b sinad = 91 . 17 d b t h d = 108 . 69 d b 16384 p o i n t ff t f i n = 1 k h z figure 8 . fft plot, 10 v range ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10k 20k 30k 40k 50k 60k 70k 80k 90k 100k amplitude (db) input frequenc y (hz) a v c c , v d r i v e = 5 v i n t e r n a l r e f e r e n c e f s a m p l e = 200 k sps t a = 2 5c 5 v r a n g e s n r = 9 0.46 d b sinad = 9 0.43 d b t h d = 1 10.74 d b 16384 p o i n t ff t f i n = 1 k h z 08938-009 figure 9 . fft plot , 5 v range ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 1k 2k 3k 4k 5k 6k amplitude (db) input frequenc y (hz) a v c c , v d r i v e = 5 v i n t e r n a l r e f e r e n c e f s a m p l e = 12.5 k sps t a = 2 5c 10 v r a n g e s n r = 100.26 d b sinad = 100.15 d b t h d = ?1 15.21 d b 16384 p o i n t ff t f i n = 131 h z 08938-109 figure 10 . fft over sampling by 16, 10 v range ?4.0 ?3.0 ?1.5 ?0.5 0.5 1.5 2.5 3.5 ?3.5 ?2.0 ?2.5 ?1.0 0 1.0 2.0 3.0 4.0 0 25,000 50,000 75,000 100,000 125,000 150,000 175,000 200,000 225,000 in l (lsb) code 250,000 08938-010 a v c c , v d r i v e = 5 v i n t e r n a l r e f e r e n c e f s a m p l e = 2 00 k sps t a = 2 5c 10 v r a n g e figure 11 . typical in l , 10 v range ?1.0 ?0.7 ?0.3 ?0.1 0.1 0.3 0.5 0.9 ?0.9 ?0.4 ?0.5 ?0.2 0 0.2 0.4 0.7 1.0 0 25,000 dn l (lsb) code 50,000 75,000 100,000 125,000 150,000 175,000 200,000 225,000 250,000 262,144 ?0.6 ?0.8 0.8 0.6 08938-011 a v c c , v d r i v e = 5 v i n t e r n a l r e f e r e n c e f s a m p l e = 2 0 0 k sps t a = 2 5c 10 v r a n g e figure 12 . typical dnl , 10 v range ?4.0 ?3.0 ?1.5 ?0.5 0.5 1.5 2.5 3.5 ?3.5 ?2.0 ?2.5 ?1.0 0 1.0 2.0 3.0 4.0 0 25,000 50,000 75,000 100,000 125,000 150,000 175,000 200,000 225,000 in l (lsb) code 250,000 08938-012 a v c c , v d r i v e = 5 v i n t e r n a l r e f e r e n c e f s a m p l e = 2 00 k sps t a = 2 5c 5 v r a n g e figure 13 . typical i nl , 5 v range www.datasheet.co.kr datasheet pdf - http://www..net/ data sheet AD7608 rev. a | page 15 of 32 ?1.0 ?0.7 ?0.3 ?0.1 0.1 0.3 0.5 0.9 ?0.9 ?0.4 ?0.5 ?0.2 0 0.2 0.4 0.7 1.0 dn l (lsb) code ?0.6 ?0.8 0.8 0.6 08938-013 a v c c , v d r i v e = 5 v i n t e r n a l r e f e r e n c e f s a m p l e = 2 00 k sps t a = 2 5c 5 v r a n g e 0 25,000 50,000 75,000 100,000 125,000 150,000 175,000 200,000 225,000 250,000 262,144 figure 14 . typical dnl , 5 v range 80 60 40 20 0 ?20 ?40 ?60 ?40 ?25 ?10 5 20 35 50 65 80 ?80 nfs error (lsb) temperature (c) 200ksps av cc , v drive = 5v external reference 5v range 10v range 08938-017 figure 15 . nfs error vs . temperature 80 60 40 20 0 ?20 ?40 ?60 ?40 ?25 ?10 5 20 35 50 65 80 ?80 pfs error (lsb) temperature (c) 200ksps av cc , v drive = 5v external reference 5v range 10v range 08938-118 figure 16 . pfs error vs . temperature 40 ?40 ?25 ?10 5 20 35 50 65 80 ?40 ?32 ?24 ?16 ?8 0 8 16 24 32 nfs/pfs channel matching (lsb) temperature (c) 10v range av cc , v drive = 5v external reference pfs error nfs error 08938-018 figure 17 . nfs/ pfs error matching 10 8 6 4 2 0 0 120k 100k 80k 60k 40k 20k ?2 pfs/nfs error (%fs) source resistance (?) av cc , v drive = 5v f sample = 200 ksps t a = 25c external reference source resistance is matched on the vxgnd input 10v and 5v range 08938-019 figure 18 . pfs/ nfs error vs . source resistance 80 85 90 95 100 105 10 100 1k 10k 100k snr (db) input frequenc y (hz) a v cc , v drive = 5v f sample changes with os r a te t a = 25c interna l reference 10v range 08938-119 os 64 os 32 os 16 os 8 os 4 os 2 no os figure 19. snr vs . input frequency for different ove rsampling rates , 10 v range www.datasheet.co.kr datasheet pdf - http://www..net/ AD7608 data sheet rev. a | page 16 of 32 80 85 90 95 100 105 10 100 1k 10k 100k snr (db) input frequenc y (hz) a v cc , v drive = 5v f sample changes with os r a te t a = 25c interna l reference 5v range os 64 os 32 os 16 os 8 os 4 os 2 no os 08938-120 figure 20. snr vs. input frequency for different oversampling rates , 5 v range ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 1k 100k 10k ?120 thd (db) input frequency (hz) 10v range av cc , v drive = 5v f sample = 200ksps r source matched on vx and vxgnd inputs 105k? 48.7k? 23.7k? 10k? 5k? 1.2k? 100? 51? 0? 08938-021 figure 21. thd vs . input frequency for various source impedances , 10 v range 1k 100k 10k thd (db) input frequency (hz) 5v range av cc , v drive = 5v f sample = 200ksps r source matched on vx and vxgnd inputs 105k? 48.7k? 23.7k? 10k? 5k? 1.2k? 100? 51? 0? ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 08938-122 figure 22 . thd vs . input frequ ency for various source impedances, 5 v range 4.0 ?40 ?25 ?10 5 20 35 50 65 80 ?4.0 ?3.2 ?2.4 ?1.6 ?0.8 0 0.8 1.6 2.4 3.2 bipolar zero code error (lsb) temperature (c) 200ksps av cc , v drive = 5v external reference 5v range 10v range 08938-023 figure 23 . bipolar zero code error vs . temperature 16 12 8 4 0 ?4 ?8 ?12 ?40 ?25 ?10 5 20 35 50 65 80 ?16 bipolar zero code error matching (lsb) temperature (c) 200ksps av cc , v drive = 5v external reference 5v range 10v range 08938-024 figure 24 . bipola r zero code error matching between channels ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 0 160 140 120 100 80 60 40 20 ?140 channel-to-channel isolation (db) noise frequency (khz) 10v range 5v range av cc , v drive = 5v internal reference AD7608 recommended decoupling used f sample = 150ksps t a = 25c interferer on all unselected channels 08938-025 figure 25 . channel - to - channel isolation www.datasheet.co.kr datasheet pdf - http://www..net/ data sheet AD7608 rev. a | page 17 of 32 80 85 90 95 100 105 1 10 no os os 2 os 4 os 8 os 16 os 32 os 64 dynamic range (db) oversampling r a tio av cc , v drive = 5v t a = 25 c internal reference f sample s c a l e s w it h o s r a t io f i n scales with os ratio 5 v r a n g e 10 v r a n g e 08938-026 figure 26 . dynamic range vs . oversampling ratio 2.5010 2.5005 2.5000 2.4995 2.4990 2.4985 ?40 ?25 ?10 5 20 35 50 65 80 2.4980 refout voltage (v) temperature (c) av cc = 4.75v av cc = 5v av cc = 5.25v 08938-129 figure 27 . reference output voltage vs . temperature for different su pply voltages 8 ?10 ?8 ?6 ?4 ?2 10 8 6 4 2 0 ?10 ?8 ?6 ?4 ?2 0 2 4 6 input current (a) input voltage (v) ?40c +25c +85c av cc , v drive = 5v f sample = 200ksps 08938-028 figure 28 . analog input current vs . input voltage across temperature 22 20 18 16 14 12 10 8 av cc supply current (ma) oversampling ratio av cc , v drive = 5v t a = 25c internal reference f sample varies with os rate no os os2 os4 os8 os16 os32 os64 08938-027 figure 29 . supply current vs . oversampling rate 140 0 1100 1000 900 800 700 600 500 400 300 200 100 60 70 80 90 100 110 120 130 power supply rejection ratio (db) av cc noise frequency (khz) av cc , v drive = 5v internal reference AD7608 recommended decoupling used f sample = 200ksps t a = 25c 10v range 5v range 08938-130 figure 30 . psrr www.datasheet.co.kr datasheet pdf - http://www..net/ AD7608 data sheet rev. a | page 18 of 32 terminology inte gral nonlinearity the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, at ? lsb below the first code transition; and full scale, at ? lsb above the las t code transition. differential nonlinearity the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. bipolar zero code error the deviation of the midscale transition (all 1s to all 0s) from the ideal, whic h is 0 v ? ? lsb. bipolar zero code error match the absolute difference in bipolar zero code error between any two input channels. positive full - scale error the deviation of the actual last code transition from the ideal last code transition (10 v ? 1? l sb (9.999 88 ) and 5 v ? 1? lsb (4.99994 )) after bipolar zero code error is adjusted out. the positive full - scale error includes the contribution from the internal reference buffer. positive full - scale error match the absolute difference in positive full - sca le error between any two input channels. negative full - scale error the deviation of the first code transition from the ideal first code transition ( ? 10 v + ? lsb ( ? 9.99996 ) and ? 5 v + ? lsb ( ? 4.9999 8 )) after the bipolar zero code error is adjusted out. the negative full - scale error includes the contribution from the internal reference buffer. negative full - scale error match the absolute difference in negative full - scale error between any two input channels. signal -to - (noise + distortion) ratio the measured ratio of signal - to - (noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency ( f s /2, excluding dc). the ratio depends on the number o f quantization levels in the digitization process ; the more levels, the smaller the quantization noise. the theoretical signal - to - (noise + distortion) ratio for an ideal n - bit converter with a sine wave input is given by signal - to - ( noise + distortio n ) = ( 6.02 n + 1.76) db thus, for an 1 8 - bit converter, the signal - to - (noise + distortion) is 110.12 db. total harmonic distortion (thd) the ratio of the rms sum of the harmonics to the fundamental. for the AD7608 , it is defined as thd (db) = 20log 1 6 5 4 3 2 v v v v v v v v v 2 9 2 8 2 7 2 2 2 2 2 + + + + + + + where: v 1 is the rms amplitude of the fundamental. v 2 to v 9 are the rms amplitudes of the second through ninth harmonics. peak harmonic or spurious noise the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2, excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is determined by a noise peak. inte rmodulation distortion (imd) with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m , n = 0, 1, 2, 3. intermodulation dist ortion terms are those for which neither m nor n is equal to 0. for example, the second - order terms include (fa + fb) and (fa ? fb), and the third - order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the calculation of the intermodulation distortion is per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels (db). power supply rejection ratio (psrr) variations in power supply affect the full - scale transition but not t he converters linearity. psr is the maximum change in full - scale transition point due to a change in power supply voltage from the nominal value. the psr ratio (psrr) is defined as the ratio of the power in the adc output at full - scale frequency, f, to th e power of a 100 mv p - p sine wave applied to the adcs v dd and v ss supplies of frequency f s . psrr (db) = 10 log ( pf / pf s ) where: pf is equal to the power at frequency f in the adc output. pf s is equal to the power at frequency f s coupled onto the av cc supp ly. channel -to - channel isolation channel - to - channel isolation is a measure of the level of crosstalk between all input channels. it is measured by applying a full - scale sin e wave signal, up to 160 khz, to all unselected input channels and then determining the degree to which the signal attenuates in the selected channel with a 1 khz sine wave signal applied (see figure 25 ). www.datasheet.co.kr datasheet pdf - http://www..net/ data sheet AD7608 rev. a | page 19 of 32 theory of operation converter details the AD7608 is a data acquisition system that employ s a high speed, low power, charge redistribution, successive approxi - mation analog - to - digital converter (adc) and allow s the simultaneous sampling of eight analog input channels. the analog inputs on the AD7608 can accept true bipolar input signals. the range pin is used to select either 10 v or 5 v as the input range. the AD7608 operate s from a single 5 v supply. the AD7608 contains input clamp protection, input signal scaling amplifiers, a second - order antialiasing filter, track - and - hold amplifiers, an on - chip refer ence, reference buffers, a high speed adc, a digital filter, and high speed parallel and serial interfaces. sampling on the AD7608 is controlled using the convst x signals. analog input analog input ranges the AD7608 can handle true bipolar, single - ended i nput voltages . the logic level on the range pin determines the analog input range of all analog input channels. if this pin is tied to a logic high, the analog input range is 10 v for all channels. if this pin is tied to a logic low, the analog input rang e is 5 v for all channels. a logic change on the range pin has an immediate effect on the analog input range; how - ever, there is typically a settling time of approximately 80 s, in addition to the normal acquisition time requirement. the recommended prac tice is to hardwire the range pin according to the desired input range for the system signals. during normal operation, the applied analog input voltage should remain within the analog input range selected via the range pin. a reset pulse must be applied after power - up to ensure the analog input channels are configured for the range selected. when in a power - down mode, it is recommended to tie the analog inputs to gnd. as per the input clamp protection section , the overvoltage clamp protection is recommen ded for use in transient overvoltage conditions and should not remain active for extended periods. stressing the analog inputs outside of the conditions mentioned here may degrade the bipolar zero code error and thd performance of the AD7608. analog input impedance the analog input impedance of the AD7608 is 1 m?. this is a fixed input impedance that does not vary with the AD7608 sampling frequency. this high analog input impedance elimi - nates the need for a driver amplifier in front of the AD7608 , allowing for direct connection to the source or sensor. wit h the need for a driver amplifier eliminated, bipolar supplies (which are often a source of noise in a system) can be removed from the signal chain. analog input clamp protection figure 31 shows the analog input structure of the AD7608 . each AD7608 analog input contains clamp protection circuitry. despite single 5 v supply operation , this analog input clamp protection allows for an input ov ervoltage up to 16.5 v. 1m? clamp vx 1m? clamp vxgnd second- order lpf r fb r fb 08938-029 figure 31 . analog input circuitry figure 32 shows the voltage vs. current characteristic of the clamp circuit. for input voltages of up to 16.5 v, no current flows in the clamp circuit. for input voltages that are above 16.5 v, the AD7608 clamp circuitry turns on. 30 ?40 ?30 ?20 ?10 0 10 20 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 input clamp current source voltage (v) 08938-030 av cc , v drive = 5v t a = 25 c figure 32 . input protection clamp profile a series resistor should be placed on the analog input channels to limit the current to 10 ma for input voltages above 16.5 v. in an application where there is a series resistance on an analog input channel, vx, a corresponding resistance is required on the analog input gnd channel, vxgnd (see figure 33 ). if there is no corresponding resistor on the vxgnd channel, an offset error occurs on that channel. 1m? clamp vx 1m? clamp vxgnd r fb r fb c r r analog input signal AD7608 08938-031 figure 33 . input resistance matching on the analog input www.datasheet.co.kr datasheet pdf - http://www..net/ AD7608 data sheet rev. a | page 20 of 32 analog input anti a liasing filter an analog antialiasing filter (a second - order butterworth) is also provided on the AD7608 . figure 34 and figure 35 show the frequency and phase response, respectively, of the analog antialiasing filter. in the 5 v range, the ?3 db frequency is typically 15 khz. in the 10 v range, the ?3 db frequency is typically 23 khz. 5 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 100 1k 10k 100k attenuation (db) input frequency (hz) 08938-135 10v range 5v range av cc , v drive = 5v f sample = 200ksps t a = 25c 10v range 0.1db 3db ?40 10,303hz 24,365hz +25 9619hz 23,389hz +85 9326hz 22,607hz 5v range 0.1db 3db ?40 5225hz 16,162hz +25 5225hz 15,478hz +85 4932hz 14,990hz figure 34 . analog antialiasing filter frequency response 08938-033 18 16 14 12 10 8 6 4 2 0 ?2 100 100k 10k 1k phase delay (s) input frequency (hz) av cc , v drive = 5v f sample = 200ksps t a = 25c 5v range 10v range figure 35 . analog antialias ing filter phase response track - and - hold amplifiers the track - and - hold amplifiers on the AD7608 allow the adc to accurately acquire an input sine wave of full - scale amplitude to 18 - bit resolution. the track - and - hold amplifiers sample their respective inputs simultaneously on the rising edge of convst x. the aperture time for track - and - hold (that is, the delay time between the external convst x signal and the track - and - hold actually going into hold) is well matched, by design, across all eight track - and - holds on one device and from device to device. this matching allows more than one AD7608 device to be sampled simultaneously in a system. th e end of the conversion process across all eight channels is indicated by the falling edge of busy; and it is at this point that the track - and - holds return to track mode, and the acquisition time for the next set of conversions begins. the conversion clock for the part is internally generated, and the conversion time for all channels is 4 s on the ad760 8 . t he busy signal returns low after all eight conversions to indicate the end of the conversion process. on the falling edge of busy, the track - and - hold am plifier s return to track mode. new data can be read from the output register via the parallel, parallel byte, or serial interface after busy goes low; or, alternatively, data from th e previous conversion can be read while busy is high. readin g data from th e AD7608 while a conversion is in progress has little e ffect on performance and allows a faster throughput to be achieved. in parallel mode at v drive > 3.3 v, the snr is reduced by ~1.5 db when reading during a conversion. adc transfer functio n the output coding of the AD7608 is twos complement. the designed code transitions occur midway between successive integer lsb values, that is, 1/2 lsb, 3/2 lsb. the lsb size is fsr/262,144 for the AD7608 . the ideal transfer characteristic for the AD7608 is shown in figure 36. 011...111 011...110 000...001 000...000 111...111 100...010 100...001 100...000 ?fs + 1/2lsb 0v ? 1lsb +fs ? 3/2lsb adc code analog input +fs midscale ?fs lsb 10v range +10v 0v ?10v 76.29v 5v range +5v 0v ?5v 38.15v +fs ? (?fs) 2 18 lsb = vin 5v ref 2.5v 5v code = 131,072 vin 10v ref 2.5v 10v code = 131,072 08938-034 figure 36 . AD7608 transfer characteristic the lsb size is dependent on the analog input range selected . www.datasheet.co.kr datasheet pdf - http://www..net/ data sheet AD7608 rev. a | page 21 of 32 internal/external re ference the AD7608 contains an on - chip 2.5 v band gap reference. the r efin/refout pin allows access to the 2.5 v reference that generates the on - chip 4.5 v reference internally, or it allows an external reference of 2.5 v to be applied to the AD7608. an externally applied reference of 2.5 v is also gained up to 4.5 v, using the internal buffer. this 4.5 v buffered reference is the reference used by the sar adc. the ref select pin is a logic input pin that allows the user to select between the in ternal reference or an external reference. if this pin is set to logic high, the internal reference is selected and enabled. if this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the refin/refout pin. the internal reference buffer is always enabled. after a reset, the AD7608 operates in the reference mode selected by the ref select pin. decoupling is required on the refin/refout pin for both the internal and external reference options. a 10 f ceramic capacitor is required on the refin/refout pin. the AD7608 contains a reference buffer configured to gain the ref voltage up to ~4.5 v, as shown in figure 37 . the refcapa and refcapb pins must be shorted together externally, and a ceramic capacitor of 10 f applied to refgnd, to ensure that the reference buffer is in closed - loop operation. the reference voltage available at the refin/refout pin is 2.5 v. when the AD7608 is configured in external reference mode, the refin/refout pin is a high input impedance pin. for applications using multiple AD7608 devices, the following configurations are recommended, depending on the application requirements. external refe rence mode one adr421 external reference can be used to drive the refin/refout pins of all AD7608 devices (see figure 38 ). in this configuration, each refin/refout pin of the AD7608 sho uld be decoupled with at least a 100 nf decoupling capacitor. internal reference mode one AD7608 device, configured to operate in the internal refer - ence mode, can be used to drive the remaining AD7608 devices, which are configured to operate in external reference mode (see figure 39 ). the refin/refout pin of the AD7608, configured in internal reference mode, should be decoupled using a 10 f ceramic decoupling capacitor. the other AD7608 devices, configured in external reference mode, should use at least a 100 nf decoupling capacitor on their refin/refout pins. buf sar 2.5v ref refcapb refin/refout refcapa 10f 08938-035 figure 37 . reference circuitry AD7608 ref select refin/refout AD7608 ref select refin/refout 100nf 0.1f 100nf AD7608 ref select refin/refout 100nf adr421 08938-037 figure 38 . single external reference driving multiple AD7608 refin pins AD7608 ref select refin/refout + 10f AD7608 ref select refin/refout 100nf AD7608 ref select refin/refout 100nf v drive 08938-036 figure 39 . internal reference driving multiple AD7608 refin pins www.datasheet.co.kr datasheet pdf - http://www..net/ AD7608 data sheet rev. a | page 22 of 32 typical connection d iagram figure 40 shows the typical connection diagram for the AD7608 . there are four avcc supply pins on the pa rt, and each of the four pins should be decoupled using a 100 nf capacitor at each supply pin and a 10 f capacitor at the supply source. the AD7608 can operate with the internal reference or an externally applied reference. in this configuration, the ad76 0 8 is configured to operate with the internal reference. when using a single AD7608 device on the board, the refin/refout pin should be decoupled with a 10 f capacitor. refer to the internal/external reference section when using an application with multiple AD7608 devices. the refcapa and refcapb pins are shorted together and decoupled with a 10 f ceramic capacito r. the v drive supply is connected to the same supply as the pro - cessor. the v drive voltage controls the voltage value of the output logic signals. for layout, decoupling, and grounding hints, see the layout guidelines section. after supplies have been applied to the AD7608 , apply a reset signal to the device to ensure it is configured for the co rrect mode of operation. power - down modes t here are t wo power - down modes available on the AD7608: standby mode and shutdown mode. the e e aa pin controls whether the AD7608 is in normal mode or in one of the two power - down modes. stby the p ower - down mode is selected through the state of the range pin when the a a stby e e aa pin is low. table 7 shows the configurations required to choose the desired power - down mode. when the AD7608 is placed in standby mod e, the current consumption is 8 ma maximum and power - up time is approximately 100 s because the capacitor on the refcapa and refcapb pins must cha rge up. in standby mode, the on - chip reference and regulators remain powered up, and the amplifiers and adc core are powered down. when the AD7608 is placed in shutdown mode, the current consumption is 11 a maximum and power - up time is approx - imately 13 ms (external reference mode). in shutdown mode, all circuitry is powered down. when the AD7608 is powered up from shutdown mode, a reset signal must be applied to the AD7608 after the required power - up time has elapsed. table 7. power - down mode selection power - down mode a a stby e e range standby 0 1 shutdown 0 0 av cc agnd v drive + refin/refout db0 to db15 convst a, b cs rd busy reset AD7608 1f 10f 100nf digital supply voltage +2.3v to +5v analog supply voltage 5v 1 eight analog inputs v1 to v8 parallel interface 1 decoupling shown on the av cc pin applies to each av cc pin (pin 1, pin 37, pin 38, pin 48). decoupling capacitor can be shared between av cc pin 37 and pin 38. 2 decoupling shown on the regcap pin applies to each regcap pin (pin 36, pin 39). regcap 2 + 10f refcapa refcapb os 2 os 1 os 0 oversampling 100nf v1 par/ser sel stby ref select range v2 v3 v4 v5 v6 v7 v8 refgnd v1gnd v2gnd v3gnd v4gnd v5gnd v6gnd v7gnd v8gnd v drive v drive microprocessor/ microconverter/ dsp 08938-038 figu re 40 . typical connection diagram www.datasheet.co.kr datasheet pdf - http://www..net/ data sheet AD7608 rev. a | page 23 of 32 conversion control simultaneous sampling on all analog input channels the AD7608 allow s simultaneous sampling of all analog input channels. all channels are sampled simul taneously when both convs t x pins (convst a, convst b) are tied together. a single convst x signal is used to control both convst x inputs. the rising edge of this common convst x signal initiates simultaneous sampling on all analog input channels . the ad760 8 contains an on - chip oscillator that is used to perform the conversions. the conversion time for all adc channels is t conv . the busy signal indicates to the user when conversions are in progress, so when the rising edge of convst x is applied, busy goes logic high and transiti ons low at the end of the entire conversion process. the falling edge of the busy signal is used to place all eight track - and - hold amplifiers back into track mode. the falling edge of busy also indicates that the new data can now be read from the parallel bus (db[15:0]), or the d out a and d out b serial data lines . simultaneously sampling two sets of channels t he AD7608 also allow s the analog input channels to be sampled simultaneously in two sets. this can be used in power - line protection and measurement sys tems to compensate for phase differences introduced by pt and ct transformers. in a 50 hz system, this allows for up to 9 of phase compensation; and in a 60 hz system, it allows for up to 10 of phase compensation. this is accomplished by pulsing the two convst x pins independently and is possible only if oversampling is not in use. convst a is used to initiate simultaneous sampling of the f irst set of channels (v1 to v4) and convst b is used to initiate simultaneous sampling on the second set of a nalo g input channels (v5 to v8) , as illustrated in figure 41 . on the rising edge of convst a, the track - and - hold amplifiers for the first set of channels are placed into hold mode. on the rising edge of convst b, the track - and - hold amplifiers for the second set of channels are placed into hold mode. the con - version process begins once both rising edges of convst x have occurred; therefore busy goes high on the rising edge of the later convst x signal. in tab le 3 , time t 5 indicates the maximum allowable time between convst x sampling points. there is no change to the data read process when using two separate convst x signals. connect all unused analog input channels to agnd. the results for any unused channel s are still included in the data read because all channels are always converted. convst a convst b busy cs, rd data: db[15:0] frstdata t 5 t conv v1 to v4 track-and-hold enter hold v5 to v8 track-and-hold enter hold AD7608 converts on all 8 channels v1 v8 v2 08938-039 figure 41 . simultaneous sampling on channel sets using independent convst a / convst b signal s parallel mode www.datasheet.co.kr datasheet pdf - http://www..net/ AD7608 data sheet rev. a | page 24 of 32 digital interface the AD7608 provide s two interface options : a parallel interface and high speed serial interface. the required interface mode is selected via the a a par e e aa /ser sel pin . the operation of the interface modes is discussed in the following sections. parallel inte rface ( par /ser sel = 0) data can be read from the AD7608 via the parallel data bus with standard a a cs e e aa and a a rd e e aa signals. to read the data over the parallel bus, the a a par e e aa /ser sel pin should be tied low. the a a cs e e aa and a a rd e e aa input signals are internally gated to enable the conversion result onto the data bus. the data lines , db 15 to db0 , leave their high impedance state when both a a cs e e aa and a a rd e e aa are logic low. AD7608 14 busy 12 rd/sclk [33:24] [22:16] db[15:0] 13 cs digital host interrupt 08938-040 figure 42 . AD7608 interface diagram one AD7608 using the parallel bus; a a cs e e aa and a a rd e e aa shorted together the rising edge of the a a cs e e aa input signal three - state s the bus and the falling edge of the a a cs e e aa input signal takes the bus out of the high impedance state. a a cs e e aa is the control signal that enables the data lines, it is the function that all ows multiple AD7608 devices to share the same parallel data bus. the a a cs e e aa signal can be permanently tied low, and the a a rd e e aa signal can be used to access the conversion results as shown in fi gure 4 . a read operation of new data can take place after the busy signal goes low ( figure 2 ), or alternatively a read operation of data from the previous conversion process can take place while busy is high ( figure 3 ). the a a rd e e aa pin is used to read data from the output conversion results register. two a a rd e e aa pulses a re required to read the full 18- bit conversion result from each channel. applying a sequen ce of 16 a a rd e e aa pulses to the AD7608 a a rd e e aa pin clocks the conversion results out from each channel onto the 16- bit parallel output bus in ascending order. the first a a rd e e aa falling edge after busy goes low clocks out d b[17:2] of the v1 result, the next a a rd e e aa falling edge updates the bus with db[1:0] of v1 result. it take s 16 a a rd e e aa pulse s to read the eight 18 - bit conversion results from the AD7608 . on the AD7608 , the 16 th falling edge of a a rd e e aa clocks out the db[1:0] conversion result for channel v8. when the a a rd e e aa signal is logic low, it enables the data conversion result from each channel to be transferred to the digital host (dsp, fpga). when there is only one AD7608 in a system/board and it does not s hare the parallel bus, data can be read using just one cont rol signal from the digital host. the a a cs e e aa and a a rd e e aa signals can be tied together as shown in figure 5 . in this cas e , the data bus comes out of three - state on the falling edge of a a cs e e aa / a a rd e e aa . the combined a a cs e e aa and a a rd e e aa signal allows the data to be clocked out of the ad7 608 and to be read by the digital host. in this case , a a cs e e aa is used to frame the data transfer of each data channel. in this case , 16 a a cs e e aa pulses are required to read the eight channels of data. www.datasheet.co.kr datasheet pdf - http://www..net/ data sheet AD7608 rev. a | page 25 of 32 serial interfa ce ( par /ser sel = 1) to read data back from the AD7608 over the serial interface, the a a par e e aa /ser sel pin should be tied high. the a a cs e e aa and sclk signals are used to transfer data from the AD7608 . the a d7608 has two serial data output pins, d out a, and d out b. data can be read back from the AD7608 using one or both of these d out lines. for the AD7608 , conversion results from channel v1 to channel v4 first appear on douta while conversion results from chann el v5 to channel v8 first appear on d out b. the a a cs e e aa falling edge takes the data output lines ( d out a and d out b ) out of three - state and clocks out the msb of the conversion result. the rising edge of sclk clocks all subsequent data bits onto the serial data outputs , d out a and d out b. the a a cs e e aa input can be held low for the entire serial read , or it can be pulsed to frame each channel read of 18 sclk cycles. figure 43 shows a read of eight simultaneous conversion results using two d out lines on the AD7608 . in this case, a 72 sclk transfer is used to access data from the AD7608 and e e aa is held low to frame the entire 72 sclk cycles. data can also be clocked out using just one d out line, in which case d out a is recommended to access all conversion data as the channel data is output in ascending order. for the AD7608 to access all eight conversion results on one d out line , a total of 144 sclk cycles are required. these 144 scl k cycles can be framed by one a a cs e e aa signal or each group of 18 sclk cycles can be individually framed by the a a cs e e aa signal. the disadvantage of using just one d out line is that the throughput rate is reduced if reading af ter conversion. the unused dout line should be left unconnected in serial mode. for the AD7608 , if doutb is used as a single dout line , the channel results will output in the fol lowing order : v5, v6, v7, v8, v1, v2, v3, v4 ; however , the frstdata indicator return s low once v5 is read on d out b. cs figure 6 shows the timing diagram for reading one channel of data, framed by the e e aa signal, from the AD7608 in serial mode. the sclk input signal provides the clock sour ce for the serial read ope ration. a a cs e e aa goes low to access the data from the AD7608. the falling edge of a a cs e e aa takes the bus out of three - state and clocks out the msb of the 18 - bit conversion result. this msb is valid o n the first falling edge of the sclk after the a a cs e e aa falling edge. the subsequent 17 data bits are clocked out of the ad7 608 on the sclk rising edge. data is valid on the sclk falling edge. eighteen clock cycles must be provided to the ad 7608 to access each conversion result. cs the frstdata output signal indicates when the first channel, v1, is bei ng read back. when the a a cs e e aa input is high , the frstd ata output pin is in three - state. in serial mode, the falling edge of a a cs e e aa takes frstdata out of three - state and sets the frstdata pin high indicating that the result from v1 is available on the d out a output data line. the frstdata output returns to a logic low following the 18 th sclk falling edge. if all chann els are read on d out b , the frstdata output does not go high when v1 is output on th e serial data output pin. it only goes high when v1 is available on d out a (and this is when v5 is available on d out b ). reading during conve rsion data can be read from the AD7608 while busy is high and conversions are in progress. this has little effect on the performance of the converter and allows a faster throughput rate to be achieved. a parallel or serial read may be performed during conversions and when oversampling ma y or may not be in use. figure 3 shows the timing diagram for reading while busy is high in parallel or serial mode. reading during conver - sions allows the full throughput rate to be achieved when using the serial interface with a v drive of 3.3 v to 5.25 v . data can be read from the AD7608 at any time other t han on the falling edge of busy because this is when the output data registers get updated with the new conversion data . time t 6 , as outlined in tabl e 3 , should be observed in this condition. v1 v4 v2 v3 v5 v8 v6 v7 sclk d out a d out b cs 72 08938-041 figure 43 . AD7608 serial interface with two d out lines www.datasheet.co.kr datasheet pdf - http://www..net/ AD7608 data sheet rev. a | page 26 of 32 digital filter the AD7608 contain s an optional digital first - order sinc filter that should be used in applications where slo wer throughput rates are used or where higher signal - to - noise ratio or dynamic range is desirable. the oversampling ratio of the digital filter is controlled using the oversampling pins, os [2:0] (see tabl e 8 ). os 2 is the msb con trol bit, and os 0 is the lsb control bit. table 8 provides the oversampling bit decoding to select the different oversample rates. the os pins are latched on the falling edge of busy. this sets the oversampling rate for the next conversion (see figure 45 ). in addition to the oversampling function, the output result is decimated to 1 8 - bit resolution. if the os pins are set to select an os ratio of 8 , the next convst x rising edge takes the first sample for each channel, and the remaining seven samples for all channels are taken with an internally generated sampling signal. these samples are then averaged to yield an improvement in snr performance. table 8 shows typical snr performa nce for both the 10 v and the 5 v range. as table 8 indicates, t here is an improvement in snr as the os ratio increases. a s the os ratio increases, the 3 db frequency is reduced, and the allowed sampling frequency is also reduce d. in an application where the required sampling frequency is 10 ksps, an os ratio of up to 16 can be used. in this case, the application sees an improvement in snr, but the input 3 db bandwidth is limited to ~6 khz. the convst a and convst b pins must be tied/driven together when oversampling is turned on. when the over - sampling function is turned on, the busy high time for the conversion process extends. the actual busy high time depends on the over sampling rate selected: the higher the oversampling rate , the longer the busy high, or total conversion time (see table 3 ) . figure 44 shows that the conversion time extends as the over - sampling rate is increased, and the busy signal lengthens for the different oversampling rates. for example, a sampling frequency of 10 ksps yields a cycle time of 100 s. figure 44 shows os 2 and os 4; for a 10 ksps example, there is adequate cycle time to further increase the oversampling rate an d yield greater improve - ments in snr performance. in an application where the initial sampling or throughput rate is at 200 ksps, for example, and oversampling is turned on, the throughput rate must be reduced to accommodate the longer conversion time and to allow for the read. to achieve the fastest throughput rate possible when over - sampling is turned on, the read can be performed during the busy high time. the falling edge of busy is used to update the output data registers with the new conversion data; therefore, the reading of conversion data should not occur on this edge. cs rd data: db[15:0] busy convst a, convst b t cycle t conv 4s t 4 t 4 t 4 9s 19s os = 0 os = 2 os = 4 08938-043 figure 44 . no oversampling, oversampling 2, and oversampling 4 while using read after conversion convst a, convst b busy os x t os_setup t os_hold conversion n conversion n + 1 oversample rate latched for conversion n + 1 08938-042 figure 45 . os pin timing table 8. over sample bit decoding os [2:0] os ratio snr 5 v r ange ( db ) 1 snr 10 v range ( db ) 1 3 db bw 5 v range (k hz ) 3 db bw 10 v range (k hz ) maximum throughput convst x frequency ( khz) 000 no os 90.5 91.2 15 22 200 001 2 92.5 93.4 15 22 100 010 4 94.45 95.7 13.7 18.5 50 011 8 96.5 98 10.3 11.9 25 100 16 99.1 100.4 6 6 12.5 101 32 101.7 102.8 3 3 6.25 110 64 103 103.5 1.5 1.5 3.125 111 invalid 1 snr values taken with a full scale 100 hz input signal. www.datasheet.co.kr datasheet pdf - http://www..net/ data sheet AD7608 rev. a | page 27 of 32 figure 46 to figure 52 illustrates the effect of over sampling on the code spread in a dc histogram plot. as the over sample rate is increased, the spread of codes is reduced. (in figure 46 to figure 52 , av cc = v drive = 5 v and the sampling rate was scaled with os ratio.) 0 200 400 600 800 1000 1200 1400 1600 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 code 1 2 3 4 5 6 7 8 9 3 3 35 82 708 1001 no oversampling 1 170 1377 1208 852 588 328 146 66 21 5 0 number of occurences 188 41 1 08938-044 figure 46 . histogram of codes no os ( 18 codes) 0 200 400 600 800 1000 1400 1800 1200 1600 2000 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 code 1 2 3 4 5 6 0 1 15 oversampling b y 2 1524 1759 1397 902 498 165 57 9 number of occurences 54 208 08938-045 538 1065 figure 47 . histogram of codes os 2 ( 14 codes) 500 0 1000 1500 2000 2500 ?5 ?4 ?3 ?2 ?1 0 code 1 2 3 4 5 oversampling b y 4 1551 2224 1913 1072 427 64 14 number of occurences 4 40 08938-046 199 684 figure 48 . histogram of codes os 4 ( 11 codes) 0 500 1000 1500 2000 2500 3000 3500 ?4 ?3 ?2 ?1 0 code 1 2 3 4 oversampling b y 8 3027 1756 457 44 2 number of occurences 4 78 08938-047 2176 648 figure 49 . histogram of codes os 8 ( 9 codes) oversampling b y 16 0 500 1000 1500 2000 3000 4000 2500 3500 4500 ?2 ?1 0 code 1 3 2 3947 385 2703 7 number of occurences 08938-148 1081 69 figure 50 . histogram of codes os 16 ( 6 codes) oversampling b y 32 0 1000 2000 3000 4000 5000 6000 ?2 ?1 0 code 1 2 5403 17 1460 number of occurences 08938-149 1301 1 1 figure 51 . histogram of codes os 32 ( 5 codes) www.datasheet.co.kr datasheet pdf - http://www..net/ AD7608 data sheet rev. a | page 28 of 32 oversampling b y 64 0 1000 2000 3000 4000 6000 5000 7000 ?1 0 code 1 number of occurences 08938-150 465 6489 1238 figure 52 . histogram of codes os 64 ( 3 codes) when the oversampling mode is selected, this has the effect of adding a digital filter function after the adc. the diff erent oversampling rates and the convst x sampling frequency produces different digital filter frequency profiles. figure 53 to figure 58 show the digital filter frequency profiles for oversampling by 2 to oversampling by 64 . the combination of the analog antialiasing filter and the oversampling digital filter can be used to eliminate or reduce the complexity of the design of the filter before the AD7608. the digital filtering combines steep roll - off and linear phase response. 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100 1k 10k 100k 10m 1m ?90 attenuation (db) frequency (hz) av cc = 5v v drive = 5v t a = 25c 10v range os by 2 08938-151 figure 53 . digital filter os 2 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100 1k 10k 100k 10m 1m ?100 ?90 attenuation (db) frequency (hz) av cc = 5v v drive = 5v t a = 25c 10v range os by 4 08938-152 figure 54 . digital filter response for os 4 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100 1k 10k 100k 10m 1m ?100 ?90 attenuation (db) frequency (hz) av cc = 5v v drive = 5v t a = 25c 10v range os by 8 08938-153 figure 55 . digital filter response for os 8 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100 1k 10k 100k 10m 1m ?100 ?90 attenuation (db) frequency (hz) av cc = 5v v drive = 5v t a = 25c 10v range os by 16 08938-154 figure 56 . digital filter response for os 16 www.datasheet.co.kr datasheet pdf - http://www..net/ data sheet AD7608 rev. a | page 29 of 32 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100 1k 10k 100k 10m 1m ?100 ?90 attenuation (db) frequency (hz) av cc = 5v v drive = 5v t a = 25c 10v range os by 32 08938-155 figure 57 . digital filter response for os 32 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100 1k 10k 100k 10m 1m ?100 ?90 attenuation (db) frequency (hz) av cc = 5v v drive = 5v t a = 25c 10v range os by 64 08938-156 figure 58 . digital filter response for os 64 www.datasheet.co.kr datasheet pdf - http://www..net/ AD7608 data sheet rev. a | page 30 of 32 layout guidelines the printed circuit board that houses t he AD7608 should be designed so that the analog and digital sections are separated and confined to different areas of the board. use at least one ground plane . it can be common or split between the digital and analog sections. in the case of the split pl ane, the digital and analog ground planes should be joined in only one place, preferably as close as possible to the AD7608 . if the AD7608 is in a system where multiple devices require analog - to - digital ground connections, the connection should still be made at only one po int: a star ground point should be established as close as possible to the AD7608 . good connections should be made to the ground plane. avoid sharing one connec - tion for multiple ground pins. individual vias or multiple vias to the ground plane should be used for each ground pin. avoid running digital lines under the devices because doing so couples noise onto the die. allow the analog ground plane to run under the AD7608 to avoid noise coupling. fast sw itching signals like convst a, convst b , or clocks sh ould be shielded with digital ground to avoid radiating noise to other sections of the board, and they should never run ne ar analog signal paths. avoid c rossover of digita l and analog signals. run t races on layers i n close proximity on the board at right angles to each other to reduce the effect of feedthrough through the board. the power supply lines to the av cc and v drive p ins on the AD7608 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. where possible , use supply planes . good connections should be made between the AD7608 supply pins and the power tracks on the board . use a single via or multiple vias for each supply pin. good decoupling is also important to lower the supply impedance presented to the AD7608 and to reduce the magnitude of the supply spikes. the decoupling capacitors should be placed close to ( ideally right up against ) these pins and their corresponding ground pins. place t he decoupling capacitors for the refin/ refou t pin and the refcapa and refcapb pins as close as possible to their respective AD7608 pins and where possible they should be placed on the same side of the board as the AD7608 device. figure 59 shows the recommended decoupling on the top layer of the AD7608 board. figure 60 shows bottom layer decoupling. bott om l ayer decoupling is for the four av cc pins and the v drive pin. 08938-051 figure 59 . top layer decoupling refin/refout, refcap a, refcapb , and regcap pins 08938-052 figure 60 . bottom layer decoupling www.datasheet.co.kr datasheet pdf - http://www..net/ data sheet AD7608 rev. a | page 31 of 32 to ensure good device - to - device performance matching, i n a system that contains multiple AD7608 devices, a symmetrical layout between the AD7608 devices is important. figure 61 sh ows a layout with two devices. the av cc supply plane runs to the right o f both devices. the v drive supply track runs to the left of the two devices. the reference chip is positioned between both the two devices and the reference voltage track runs north to pin 42 of u1 and south to pin 42 to u2. a solid ground plane is used . these symmetrical layout principles can be applied to a system that contains more than two AD7608 devices. the AD7608 devices can be placed in a north - s outh direction with the reference voltage located midway between the AD7608 devices with the refer enc e track running in the north - south direction similar to figure 61. avcc u2 u1 u2 u1 08938-053 figure 61 . layout for multiple AD7608 devices top layer and supply plane layer www.datasheet.co.kr datasheet pdf - http://www..net/ AD7608 data sheet rev. a | page 32 of 32 outline dimensions compliant t o jedec s t andards ms-026-bcd 051706- a t op view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc lead pitch 12.20 12.00 sq 1 1.80 pin 1 1.60 max 0.75 0.60 0.45 10.20 10.00 sq 9.80 view a 0.20 0.09 1.45 1.40 1.35 0.08 coplanarit y view a ro ta ted 90 ccw se a ting plane 0.15 0.05 7 3.5 0 figure 62 . 64 - lead low profile quad flat package [lqfp] (st - 64- 2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD7608 bstz ?40c to +85c 64- lead low profile quad flat package [lqfp] st -64-2 AD7608 bstz -rl ?40c to +85c 64- lead low profile quad flat package [lqfp] st -64-2 eval - AD7608 edz ?40c to +85c evaluation board for the AD7608 ced1z converter evaluation development 1 z = rohs compliant part. ? 2011 - 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08938 - 0- 1/12(a) www.datasheet.co.kr datasheet pdf - http://www..net/ |
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